MAX1159AEUI+【PDF 2/15 页】IC ADC 14BIT 135KSPS 28-TSSOP

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Sheet目录2008

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MAX1157/MAX1159/MAX1175

Shutdown Mode

In shutdown mode, the reference and reference buffer

shut down between conversions. Shutdown mode

reduces supply current to 0.5A (typ) immediately after

the conversion. The next falling edge of CS with R/C

low causes the reference and buffer to wake up and

enter acquisition mode. To achieve 14-bit accuracy,

allow 12ms (CREFADJ = 0.1F, CREF = 10F) for the

internal reference to wake up.

Internal and External Reference

Internal Reference

The internal reference of the MAX1157/MAX1159/

MAX1175 is internally buffered to provide +4.096V out-

put at REF. Bypass REF to AGND and REFADJ to

AGND with 10F and 0.1F, respectively.

Sink or source current at REFADJ to make fine adjust-

ments to the internal reference. The input impedance of

REFADJ is nominally 5k

. Use the circuit of Figure 7 to

adjust the internal reference to ±1.5%.

External Reference

An external reference can be placed at either the input

(REFADJ) or the output (REF) of the MAX1157/

MAX1159/MAX1175’s internal buffer amplifier. Using

the buffered REFADJ input makes buffering the external

reference unnecessary. The input impedance of

REFADJ is typically 5k

. The internal buffer output

must be bypassed at REF with a 10F capacitor.

Connect REFADJ to AVDD to disable the internal buffer.

Directly drive REF using an external 3.8V to 4.2V refer-

ence. During conversion, the external reference must

be able to drive 100A of DC load current and have an

output impedance of 10

or less.

For optimal performance, buffer the reference through

an op amp and bypass REF with a 10F capacitor.

Consider the MAX1157/MAX1159/MAX1175’s equivalent

input noise (0.6LSB) when choosing a reference.

Reading the Conversion Result

EOC flags the microprocessor when a conversion is

complete. The falling edge of EOC signals that the data

is valid and ready to be output to the bus. D0–D13 are

the parallel outputs of the MAX1157/MAX1159/

MAX1175. These three-state outputs allow for direct

connection to a microcontroller I/O bus. The outputs

remain high-impedance during acquisition and conver-

sion. Data is loaded onto the bus with the third falling

edge of CS with R/C high (after tDO). Bringing CS high

forces the output bus back to high impedance. The

MAX1157/MAX1159/MAX1175 then wait for the next

falling edge of CS to start the next conversion cycle

(see Figure 2).

14-Bit, 135ksps, Single-Supply ADCs with

Bipolar Analog Input Range

______________________________________________________________________________________

Figure 6. Selecting Shutdown Mode

R/C

EOC

REF AND

BUFFER

POWER

ACQUISITION

CONVERSION

DATA

OUT

Figure 7. MAX1157/MAX1159/MAX1175 Reference Adjust

Circuit

MAX1157

MAX1159

MAX1175

REFADJ

+5V

68k

100k

150k

0.1

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